1. Field of the Invention
The present invention relates to a semiconductor integrated circuit and a method for controlling a semiconductor integrated circuit.
2. Background Art
Semiconductor integrated circuits have been remarkably improved to be more multifunctional and highly integrated in recent years. In such a semiconductor integrated circuit, multiple functional circuits (intellectual property (IP) circuits) implementing different functions are monolithically integrated.
Multiple master circuits and multiple slave circuits are generally mounted in such a multifunctional semiconductor integrated circuit. A master circuit is a circuit that instructs other circuits to execute given processing. Examples of a master circuit include a central processing unit (CPU), a digital signal processor (DSP) and other signal-processing circuits (such as an image processing circuit). On the other hand, a slave circuit is a circuit that executes a given processing in response to an instruction issued by others. An example of a slave circuit is a semiconductor storage device (hereinafter referred to as a memory when appropriate).
Systems each including master circuits and slave circuits are disclosed in Japanese Patent Application Publication Nos. Hei 6-274459, 2003-296294, 2001-166960, and Hei 2-85953. In a technique disclosed in Japanese Patent Application Publication No. Hei 6-274459, the connection relation between processors is allowed to be changed, so that the versatility of LSI is improved. In a technique disclosed in Japanese Patent Application Publication No. 2003-296294, an input/output terminal is assigned to one of multiple function modules on the basis of profile data that indicates whether each of the function modules is used or not. In a technique disclosed in Japanese Patent Application Publication No. 2001-166960, an individual region for each processor is assigned to a shared memory. Japanese Patent Application Publication No. Hei 2-85953 discloses a technique for performing a fault analysis on a master module.
In some semiconductor integrated circuits each including master circuits and slave circuits, a given slave circuit is previously assigned to a given master circuit. In this case, the slave circuit assigned to the master circuit is unavailable when the master circuit is in an inactive state (in a shutdown state or a sleep state).
In a semiconductor integrated circuit including multiple master circuits and multiple slave circuits, the number of unavailable slave circuits increases as the number of master circuits in an inactive state increases. This may result in a significant decrease in the use efficiency of system resources. In other words, a slave circuit assigned to a certain master circuit becomes unavailable when the certain master circuit goes into an inactive state. Accordingly, the use efficiency of system recourses decreases.